The present invention relates in general to wafer fabrication. More particularly, the present invention relates to wafer fabrication processes in which a fully aligned via (FAV) is formed with integrated air gaps.
The fabrication of very-large scale integrated (VLSI) or ultra-large scale integrated (ULSI) circuits requires an interconnect structure including metallic wiring that connects individual devices in a semiconductor chip to one another. Typically, the wiring interconnect network includes two types of features that serve as electrical conductors. These are line features that traverse a distance across the chip and via features which connect lines in different levels. Typically, the conducting metal lines and vias are formed of aluminum or copper and are insulated by the interlayer dielectrics (ILD) which are electrical insulators.